(a) Field of the Invention
The present invention relates generally to wrapped core linking module (WCLM) for accessing system on chip (SoC) test and, more particularly, to WCLM for systematically accessing a SoC test in which not only IEEE 1149.1 boundary scan but also cores embodied by an IEEE P1500 wrapper maintain compatibility with the IEEE 1149.1 standard and have expandability.
(b) Description of the Related Art
In general, there were a plurality of proposed methods using the prior test board of the IEEE 1149.1 standard for testing SoC comprising IP cores, which are shown in FIG. 1 through FIG. 6.
The structure for accessing SoC test serially connected to test data in (TDI) and test data out (TDO) shown in FIG. 1 is serial connection method of all TAPs between TDI and TDO. The structure always has the maximum length of the scan path because all TAPs are activated in case of test mode. In view of chip level, said structure for accessing SoC test violates the IEEE 1149.1 standard due to the all activated TAPs.
The structure for accessing SoC test with dedicated selection pins shown in FIG. 2 is a method of adding the selection pins, which each pin selects TAP. Due to select TAP1 in the SoC test and one of TAP2 through TAP4 in case of core test, the number of the selection pins increases in proportion to the increasing number of TAP. However, said structure for accessing SoC test with the dedicated selection pins has a problem unable to select a group of TAP.
Also, the processor core with an IEEE 1149.1 and a debugging register shown in FIG. 3 as the method proposed by IBM uses to debug processor core embedding the debugging register.
That is, the method places the processor cores serially connected to the TAPs using an IEEE 1149.1 in SoC and processor core on the scan path in case of test mode so that it is able to access to the debugging register in the processor cores (P1˜P3) The method has a problem disable to check linking line between the processor cores and the boundary scan register, ICBSR, because there is only one test data register between TDI and TDO.
In addition, the structure for accessing SoC test with TLM shown in FIG. 4 as the method proposed by TI is able to dynamically connect all TAPs using TAP linking module. The operation as the default to make TAP1 such as SoC TAP activated places TAP1 on the scan path of TDI and TDO. Thus, it satisfies the IEEE 1149.1 standard in chip level.
If said structure for accessing SoC test with TLM inactivates TAP1 and TAP4 and activates TAP2 and TAP3 for testing core and places them on the scan path of TDI and TDO, it inserts a link_update instruction to the activated TAP1 and SEL signal from TAP1 is applied to TLM in order that TLM updates link configuration. Then the link configuration of TLM is updated by TDI and TMS input.
If the link configuration is updated, enabled ENA (ENA=‘1’) from the TLM applied to TAPs (TAP2 and TAP3) to activate and disabled ENA (ENA=‘0’) from the TLM applied to TAPs (TAP1 and TAP4) to inactivate. TAP2 and TAP3 are placed on the scan path of TDI and TDO so that the linking line between cores can be checked.
At this point, TAP1 and TAP4 excluded in the scan path of TDI and TDO keep the stable RunTest/Idle state. Due to adding SEL and ENA signals and the link_update instruction to each standard TAPs, the architecture of the provided IP and the standard TAP needs to change.
The structure for accessing SoC test with modified TLM shown in FIG. 5 as a method proposed by TI to solve TLM's problem is not necessary to change the architecture of IP core, which is the principle problem of the TLM method proposed by TI. Therefore, the structure for accessing SoC test with modified TLM is able to use the provided IP core and enables the dynamically various links of cores with TAPs.
To obtain this, a module called a state condition expander (SCE) was added in each TAP. The operation of the module as a default activates TAP1 such as SoC TAP and places the TAP1 on the scan path of TDI and TDO. Thus, the operation satisfies the IEEE 1149.1 standard in chip level.
If said structure for accessing SoC test with modified TLM inactivates TAP1 & TAP4 and activates TAP2 & TAP3 for testing cores placed on the scan path of TDI-TDO and applies SEL_TLM=‘1’ of SoC, said TLM is placed on the scan path of TDI-TDO in SoC and then the link configuration of TLM is updated by TDI and TMS inputs.
At this point, all TAPs are on the stable RunTest/Idle state. After updating the link configuration, the activated TAP2 and TAP3 are synchronized with a test bus of SoC and have state transition. TAP1 and TAP4 excluded on the scan path of TDI-TDO keep the stable Run Time/Idle state. If the method is hierarchically used as allocating of additional pins to SoC, the number of pins increases in proportion to the additional pins.
The method of hierarchical TAP (HTAP) shown in FIG. 6 is another method proposed by TI. The HTAP comprises mainly a programmable switch and Snoopy-TAP (SN-TAP).
Said programmable switch provides dynamically various links to TAPs of each core and plays a role of placing on the path of TDI-TDO in SoC. That is, as the compatible 1149.1 TAP of SoC, said programmable switch operates by the 1149.1 standard TAP on a board in chip test. In case of testing core in SoC, said programmable switch plays a role of an intermediary in order that cores of each TAP use a test bus of the SoC.
Said HTAP method solves defects of both the prior TLM method and an ad-hoc method. Because an additional TAP controller of said HTAP method is not necessary for a module to update link configuration between cores as that of a TLM method needed, the power and area overhead of said HTAP method decreases. Said HTAP method changes the mode bit of a control register in SN-TAP as ‘1’ so that the SN-TAP such as SoC TAP enters into the Snoopy state for core test. Thus, said HTAP method enables TMS (TMS=‘0’) when the down edge of TCK in said HTAP method is on the Update-DR state.
Said SN-TAP enters not into the RunTest/Idle state of the 1149.1 standard but into the SN-TL-Reset state, which uses separate state transition besides the state transition of the IEEE 1149.1 standard TAP controller. Thus, the state transition is unnatural in view of state transition of the IEEE 1149.1 standard TAP. Also, It requires for a test engineer to have a clear knowledge about additional operations besides the IEEE 1149.1 standard operation. However, the HTAP method is required to change an 1149.1 standard TAP controller of SoC and it is necessary to have an additional register to control. Also, there was a problem unable to check a linking line between ICBSR and CBSR.